1. Field of Invention
This invention relates to an abrasive construction having abrasive, rigid, and resilient elements for modifying an exposed surface of a semiconductor wafer.
2. Description of the Related Art
In the course of integrated circuit manufacture, a semiconductor wafer typically undergoes numerous processing steps, including deposition, patterning, and etching steps. Additional details on how semiconductor wafers are processed can be found in the article "Abrasive Machining of Silicon" by Tonshoff, H. K.; Scheiden, W. V.; Inasaki, I.; Koning, W.; Spur, G. published in the Annals of the International Institution for Production Engineering Research, Volume 39/2/1990, pages 621 to 635. At each step in the process, it is often desirable to achieve a pre-determined level of surface "planarity" and/or "uniformity." It is also desirable to minimize surface defects such as pits and scratches. Such surface irregularities may affect the performance of a final patterned semiconductor device.
One accepted method of reducing surface irregularities is to treat the wafer surface with a slurry containing a plurality of loose abrasive particles using a polishing pad. An example of a polishing pad for use with a slurry is described in U.S. Pat. No. 5,287,663 (Pierce et al.). This pad includes a polishing layer, a rigid layer adjacent the polishing layer, and a resilient layer adjacent the rigid layer. The polishing layer is material such as urethane or composites of urethane.